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The Gate Delay Analysis Method Accounting for Simultaneous Input Switching
Authors
	Gavrilov S.V.
	Gudkova O.N.
	Pirutina G.A.
Date of publication
	2012
Abstract
	A wide set of digital circuit simulation problems requires both maximal node delay and minimal delay. The accurate minimal delay model depends on glitches and simultaneous gate input switching. But the existing logic level performance analysis tools, as a rule, use simplified pin-to-pin- gate delay model. This paper describes the method, which provides considerable logic level delay analysis accuracy versus the famous approaches accounting for the simultaneous multiple input switching.
Keywords
	Static timing analysis (STA), gate delay, SP-DAG, static timing analysis, intellective property block (IP-block).
Library reference
	Gavrilov S.V., Gudkova O.N., Pirutina G.A. The Gate Delay Analysis Method Accounting for Simultaneous Input Switching // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 119-124.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D19.pdf