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SystemVerilog object-oriented programming features for functional verification of multi-core SoC
Authors
	Putrya F.M.
Date of publication
	2012
Abstract
	It is known that the functional verification has become the most complicated and expensive step in the development of modern multicore systems on chip (SoC). For this reason, the introduction of route development SoC new tools and techniques that accelerate the verification process is a priority. Features PLO pledged in SystemVerilog and created on the basis of these features verification libraries, such as UVM can greatly simplify development and verification environments and tests for SoC. The article discusses some aspects of these technologies, as well as the proposed solution to standardize and use the platform approach to test development and also reference C++ model of SoC blocks.
Keywords
	functional verification, SystemVerilog, PLO, UVM, transaction level, reference model
Library reference
	Putrya F.M. SystemVerilog object-oriented programming features for functional verification of multi-core SoC // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 83-88.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D18.pdf