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VHDL-Simulation-Based Evaluation of CMOS-Circuits Power Consumption
Authors
	Bibilo P.N.
	Soloviev A.L.
Date of publication
	2012
Abstract
	We consider the problem of power consumption evaluation for circuits synthesized from the custom-ASIC CMOS logic circuits design library. It is proposed to estimate the power consumption by the high-speed logic VHDL-simulation according to descriptions of the circuits. The experimental results show a significant decrease of simulation time and acceptable accuracy in comparison with the results of time-consuming circuit simulation.
Keywords
	Computer-aided design, ASIC, CMOS technology, simulation, logic circuits, VHDL, switching activity.
Library reference
	Bibilo P.N., Soloviev A.L. VHDL-Simulation-Based Evaluation of CMOS-Circuits Power Consumption // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 39-42.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D2.pdf