Synchronous elastic circuits design and its application for H.264 CABAC decoder performance optimization

Gotmanov, A.N.; Kishinevsky, M.A.; Galceran-Oms, M.

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Authors

Gotmanov A.N.

Kishinevsky M.A.

Galceran-Oms M.

Date of publication

2010

Abstract

Specifications of synchronous circuits typically rely on fixed latencies of computations
and communications. This makes the design process fragile and leaves out optimization opportunities
(one needs to optimize all data cases even if they rarely occur). As we illustrate in a design
experiment with the critical block of H.264 video decoder, latency tolerant implementation can
achieve x1.5 performance increase with no penalty to area/power. We developed a new method for
designing variable latency units and a prototype CAD technology to partially automate conversion of
existing RTL to latency tolerant (elastic) form and further optimize it by applying provably correct
microarchitectural transformations.

Keywords

performance optimization, hardware, latency tolerance, elasticity, video coding,
H.264, CABAC.

Library reference

Gotmanov A.N., Kishinevsky M.A., Galceran-Oms M. Synchronous elastic circuits design and its application for H.264 CABAC decoder performance optimization // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 8-13.

URL of paper

http://www.mes-conference.ru/data/year2010/papers/m10-146-99991.pdf