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| An Algorithm for determining the size of transistors, based on statistical static timing analysis |
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| Authors |
| | Melikyan V.Sh. |
| | Mirzoyan D.L. |
| | Petrosyan G.A. |
| | Aharonyan V.K. |
| Date of publication |
| | 2010 |
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| Abstract |
| | Due to variations in parameters of technological processes in submicron technologies, large delay variations of integrated circuits (ICs) that affect the efficiency ratio of IP are observed. An algorithm for determining the size of logic elements in assessing the variation of delay circuits, using statistical static timing analysis (SSTA)with consideration of intra-circuit and inter-circuit variations and gauging the size of logic elements to achieve the desired output rate is presented. |
| Keywords |
| | Algorithm efficiency ratio, static timing analysis. |
| Library reference |
| | Melikyan V.Sh., Mirzoyan D.L., Petrosyan G.A., Aharonyan V.K. An Algorithm for determining the size of transistors, based on statistical static timing analysis // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 114-119. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-26-25052.pdf |
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