| Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array |
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| Authors |
| | Stepchenkov Yu.A. |
| | Petrukhin V.S. |
| | Diachenko Yu.G. |
| Date of publication |
| | 2005 |
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| Abstract |
| | State and design problems of strictly self-timed (SST) electronic circuits are considered. SST-circuits are "naturally reliable" as they guarantee preservation of capacity for work of the device in the wide range of environment conditions comparable to the physical restrictions for integrated circuits. The SST-circuitry to the full meets the requirements, showed to element base for critical areas of applications.
This article is devoted to development of effective means for designing and fabrication the SST-VLSI on home Gate Array (GA) 5503 basis. The preliminary results of the development (after simulation and topological design on native industrial CAD for basic gate-array “Kovcheg 2.6”) of synchronous and SST-variants of test silicon “Microcore” are presented. This silicon implements functions of 8-bit microcontroller PIC18CXX (widely used in manufactured in Russia devices) computational core. |
| Keywords |
| | Self-timed circuit; gate array; programmable logical device; test |
| Library reference |
| | Stepchenkov Yu.A., Petrukhin V.S., Diachenko Yu.G. Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array // Problems of Perspective Microelectronic Systems Development - 2005. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2005. P. 235-242. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2005/35.doc |
