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Optimized for Sub-micron Processes A High Speed ADC Architecture
Authors
	Agrich Yu.V.
	Lifshits V.B.
Date of publication
	2010
Abstract
	Optimized for sub micron processes flash – pipelined architecture of the high speed precision CMOS ADC with reduced pipeline stage signal and calibration is presented. Input flash stage includes flash ADC, DAC with string resistive divider and double sampling sample-hold unit which produces doubled difference of input signal and DAC output. Flash stage can operate at reference voltage and input signal up to supply voltage. Pipeline stages use 1.5-bit RSD with decreased reference voltage. Flash and RSD stages output signal is reduced to increase speed and decrease power. Simulation of the 12-bit ADC based on 180nm process presents sampling rate up to 167Msps and conversion energy 200fJ/bit. The 12-bit ADC has active area 0,75 sq.mm.
Keywords
	High speed ADC, flash ADC, pipelined ADC, track-and-hold unit, TH, RSD stage, conversion energy per effective bit, FOM.
Library reference
	Agrich Yu.V., Lifshits V.B. Optimized for Sub-micron Processes A High Speed ADC Architecture // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 497-502.
URL of paper
	http://www.mes-conference.ru/data/year2010/papers/m10-136-76643.pdf