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The static accuracy model for the pipelined ADC with calibration
Authors
	Lifshits V.B.
	Agrich Yu.V.
Date of publication
	2010
Abstract
	The model suggested allows the quick estimating of the process factors affect to the static accuracy of the pipelined ADC with calibration before start of schematic design. The dominant sources of errors are considered. A practical design of the 12-bits ADC on 180 nm process is the source of example
Keywords
	ADC, DAC, Sample/Hold, correction, calibration, flash, RSD, INL, DNL
Library reference
	Lifshits V.B., Agrich Yu.V. The static accuracy model for the pipelined ADC with calibration // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 527-532.
URL of paper
	http://www.mes-conference.ru/data/year2010/papers/m10-135-19281.pdf