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| Optimization for some phase of Komdiv64-RIO design flow |
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| Authors |
| | Evlampiev B.E. |
| | Vlasov A.O. |
| | Kirichenko P.G. |
| | Kochnov A.A. |
| Date of publication |
| | 2010 |
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| Abstract |
| | This paper contains descriptions of the following questions: area optimization with keeping of performance during synthesis, building of power grid, automation of performance increase at the layout stage, optimization of layout design. |
| Keywords |
| | synthesis, power grid, clock shift, hierarchical implementation flow |
| Library reference |
| | Evlampiev B.E., Vlasov A.O., Kirichenko P.G., Kochnov A.A. Optimization for some phase of Komdiv64-RIO design flow // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 394-399. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-233-31111.pdf |
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