| High level model based verification of digital circuits behavior |
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| Authors |
| | Shcherbakov A.S. |
| Date of publication |
| | 2010 |
|
| Abstract |
| | A significant part of modern electronic schematic commonly consists from sets of large units (block) reused from previous implementations with some additions of new features and/or optimizations. Here, a problem of such blocks behavioral equivalence proof against an abstract
high level model (HLM) is considered. Requirements applicable to languages used for such
models scribing are enumerated, particularly concerning Murphi language. An overview is given on major difficulties occurring in formal verification of electronic logic designs against HLM’s. A method taking advantage of event based refinement is described. |
| Keywords |
| | high level models; abstract models; behavioral models; logic circuits; Murphi; formal
verification. |
| Library reference |
| | Shcherbakov A.S. High level model based verification of digital circuits behavior // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 42-47. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-148-27781.pdf |
