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| IP-core of High-Speed Low-Power ADC for multi-channel SoC |
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| Authors |
| | Butuzov V.A. |
| | Bocharov Y.I. |
| | Gumenyuk A.S. |
| | Osipov D.L. |
| | Simakov A.B. |
| | Atkin E.V. |
| Date of publication |
| | 2010 |
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| Abstract |
| | The techniques of reducing energy consumption CMOS pipelined ADC are proposed. The methods are based on the sharing of amplifiers and comparators by the adjacent stages. The example of the practical implementation of these methods to develop low power 9-bit 20MHz pipelined ADC IP-core for the multi-channel signal processing systems is presented. |
| Keywords |
| | ADC, IP-core, SoC, CMOS |
| Library reference |
| | Butuzov V.A., Bocharov Y.I., Gumenyuk A.S., Osipov D.L., Simakov A.B., Atkin E.V. IP-core of High-Speed Low-Power ADC for multi-channel SoC // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 517-520. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-113-59881.pdf |
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