| Polygons size and form optimization in layout compaction process |
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| Authors |
| | Plehanov A.S. |
| Date of publication |
| | 2010 |
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| Abstract |
| | Optimization method of improving forms and the sizes of conductors is offered. This method applied in topology compaction process. The method is used in submicron topologies to which conductors are presented in the form of polygons. |
| Keywords |
| | layout compaction, circuit performance optimization, polygon-based layout description |
| Library reference |
| | Plehanov A.S. Polygons size and form optimization in layout compaction process // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 200-203. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-4-94621.pdf |
