| Voronoi diagram based graph models building in VLSI physical design |
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| Authors |
| | Malinauskas K.K. |
| Date of publication |
| | 2008 |
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| Abstract |
| | A unified abstract Voronoi diagram based approach to build diverse graph models in physical design systems is proposed. It is applied to building the three independent graph models for layout compaction and legalization, global routing and wire length estimation, mask-to-symbolic layout conversion. It is shown that several problems are solved simultaneously: model quality and redundancy, effective build and local update. The generality of the approach enables the code reuse in representation and build of different graph models in physical design. |
| Keywords |
| | VLSI physical design, Voronoi diagram, graph models |
| Library reference |
| | Malinauskas K.K. Voronoi diagram based graph models building in VLSI physical design // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2008. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2008. P. 114-119. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2008/17.pdf |
