CELLERITY: THE SYSTEM OF AUTOMATIC SYNTHESIS OF STANDARD CELL LAYOUT

Zinchenko, L.A.; Mazias, R.L.; Rozenfeld, V.P.; Smirnov, Yu.G.; Sotnikov, M.A.; Stoyanov, S.V.; Topuzov, I.G.; Falkovsky, K.D.

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Authors

Date of publication

2005

Abstract

One of effective methods of designing CMOS IC is based on the use of standard cell libraries. Thus large IC blocks are built of so-called standard cells implementing various logic functions (NAND, AOI, multiplexer, flop-flop). Standard cells of the library have a number of common properties facilitating designing block layouts: cell height, location of supply rails, and others. Standard cells layout design used to be done manually for a long time. However, in the middle of 90th, CAD systems solving this problem automatically began to appear. It had been caused by the factors related mainly with the rapidly changing IC market, feature size reduction and consequently with complication of process technology rules, increased number of cells in the library, need to supplement available libraries with new cells specific to ICs of various purpose and performance.
In this paper CELLERITY, the automatic layout synthesis system for standard cell libraries, developed in Freescale Semiconductor is considered. This system supports process technologies with the minimal gate sizes down to 0.06 microns, and it is used for creation of libraries of various architectures.

Keywords

automatic layout synthesis, standard cell

Library reference

Zinchenko L.A., Mazias R.L., Rozenfeld V.P., Smirnov Yu.G., Sotnikov M.A., Stoyanov S.V., Topuzov I.G., Falkovsky K.D. CELLERITY: THE SYSTEM OF AUTOMATIC SYNTHESIS OF STANDARD CELL LAYOUT // Problems of Perspective Microelectronic Systems Development - 2005. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2005. P. 113-120.

URL of paper

http://www.mes-conference.ru/data/year2005/17.doc