| Hardware Implementation of an Accelerated Approximated Matrix Multiplier Based on MADDNESS Algorithm |
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| Authors |
| | Zhigulin A.S. |
| | Solovyev R.A. |
| Date of publication |
| | 2022 |
| DOI |
| | 10.31114/2078-7707-2022-4-94-100 |
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| Abstract |
| | The article proposes a technique for creating of hardware implementation of an accelerated approximated matrix multiplier MADDNESS. This multiplier has good performance in terms of accuracy and speed and at same time is distinguished by simplicity of the decoder. As a result of the research, it was possible to achieve a very high speed of the multiplier at the hardware level by rejection of the multiplication operation as such. At the same time, the quality of the obtained prediction remains high. |
| Keywords |
| | Hardware implementation of matrix multiplying, FPGA, integer arithmetic. |
| Library reference |
| | Zhigulin A.S., Solovyev R.A. Hardware Implementation of an Accelerated Approximated Matrix Multiplier Based on MADDNESS Algorithm // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 4. P. 94-100. doi:10.31114/2078-7707-2022-4-94-100 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2022/pdf/D062.pdf |
