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Implementation of Area Optimal FIR Filters Based on Lookup Tables for Sigma-Delta Modulator Signal Processing
Authors
	Skripnichenko M.N.
Date of publication
	2022
DOI
	10.31114/2078-7707-2022-3-140-145
Abstract
	The article proposes an implementation option for FIR filters for a multi-stage sigma-delta ADC architecture using lookup tables. Examples of splitting such a filter into subtables are given and the minimum area variant is shown. The sigma-delta ADC is one of the most widely used analog-to-digital converters. The classic converter architecture shown includes a modulator and a digital decimator. Recently there has been an increased interest on the MASH architecture with each stage having separate modulator outputs that require a separate digital decimation filter. In connection with the increase in the number of digital filters, the task of reducing the area occupied by them becomes relevant. In the case of the classical implementation of FIR filters, a set of adders is required to add or subtract the decimation/reconstruction filter coefficients depending on the one-bit signal coming from the comparator output. The author proposes the implementation of the filter using conversion tables, in the lines of which there are already pre-calculated and summed up in the required way weight coefficients. Here is an example of the implementation of a four-input table for input signals IN[0], IN[-1], IN[-2], IN[-3] and their corresponding weight coefficients W0, W1, W2, W3: for the values IN[0:-3 ]=0000 the result is -W0-W1-W2-W3, for IN[0:-3]=0001 the result is -W0-W1-W2+W3, and so on. A program that takes the coefficients of the FIR filter as input and returns the sets of recoding tables described on SystemVerilog and an adder that adds the outputs of these tables was developed. It is difficult to implement a multi-input table, the delay of which would fit into the period of the clock signal of the digital part. Therefore, the paper proposes to “split” one recoding table into several small ones, followed by summing up the results. In this regard, it is important to conduct a study on the optimal number of entries in a small table to minimize the occupied area. It is shown that the most optimal in terms of area is partitioning into six-input tables, and their use allows reducing the occupied area by 20.12% compared to the classical architecture.
Keywords
	sigma-delta ADC, FIR filters, Look up tables, decimation.
Library reference
	Skripnichenko M.N. Implementation of Area Optimal FIR Filters Based on Lookup Tables for Sigma-Delta Modulator Signal Processing // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 3. P. 140-145. doi:10.31114/2078-7707-2022-3-140-145
URL of paper
	http://www.mes-conference.ru/data/year2022/pdf/D052.pdf