| DC-DC Converter Conducted Emission Level Estimation at Design Stage |
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| Authors |
| | Belyaev A.A. |
| | Shchuchkin E.Yu. |
| Date of publication |
| | 2022 |
| DOI |
| | 10.31114/2078-7707-2022-3-66-73 |
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| Abstract |
| | In modern systems electronic devices simultaneously send data via digital high-speed interfaces and cause impulse current consumption. This creates electromagnetic interference in the form of conducted emission through common power circuits or through parasitic connections and can disrupt the system performance. Modern DC-DC converters are required to have electromagnetic compatibility, because they are the most common sources of emission for external nets. To meet the standards requirements developers use special circuit solutions and input filters. To properly design an input filter the designer needs to know the conducted emission profile created by the DC-DC converter. At the schematic design stage traditional circuit simulation does not take into account parasitic components of a printed circuit board. If the layout parasitic parameters extraction results are not satisfactory, then a designer will have to make changes to the schematic or layout, which can take a long time. In this paper proposed an approach to determining the profile of conducted emission based on a microstrip line simplified model of Hammerstad-Jensen. The method described in the paper allows to heuristically estimate the parasitic parameters of interconnections based on the conductors lengths between the PCB components and the technological stack parameters at the schematic design stage. Conductors length values can be obtained from the layout reference design library based on the PWM controllers datasheets. The study presents the conducted emission profile comparison as a result of the traditional SPICE simulation, simulation according to the proposed method and the profile obtained as a result of DC-DC converter characteristics measurements in the EMC laboratory. The method proposed in the article made it possible to detect the harmonic components of conducted emission in the megahertz frequency range at the stage of schematic design. This reduces the probability of the circuit correction after layout extraction and helps to avoid additional EMC testing in laboratory. |
| Keywords |
| | EMC, conducted EMI, DC-DC converter, interconnect parasitic elements. |
| Library reference |
| | Belyaev A.A., Shchuchkin E.Yu. DC-DC Converter Conducted Emission Level Estimation at Design Stage // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 3. P. 66-73. doi:10.31114/2078-7707-2022-3-66-73 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2022/pdf/D045.pdf |
