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| Exact Synthesis of Low Precision Multipliers for Intel FPGAs |
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| Authors |
| | Shupletsov M.S. |
| | Zhukov V.V. |
| | Gribok S.V. |
| | Ganusov I. |
| | Mestetskiy M.A. |
| | Lopunov M.A. |
| | Kuprash E.D. |
| Date of publication |
| | 2022 |
| DOI |
| | 10.31114/2078-7707-2022-3-212-218 |
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| Abstract |
| | Building efficient FPGA-based AI inference accelerators sets new requirements for FPGA compilers. AI inference accelerator contains very large amount of very small identical circuits (such as low precision multipliers). So, in order to maximize the overall accelerator performance, it is very important to build those small circuits optimally (in terms of area and delay). SAT-based exact synthesis is known to be an efficient technique to build optimal LUT-based circuits for logic functions with a small number of inputs.
In this paper we extend exact synthesis methods to support FPGA Adaptive Logic Module (ALM) structure. We present a SAT-based exact synthesis tool that builds optimal Stratix 10 and Agilex ALM-based circuits. We use the tool to build optimal FPGA circuits for low-precision multipliers and demonstrate that the new circuits are 10-50% more area-efficient if compared with circuits generated by Quartus Compiler. Furthermore, we demonstrate that our approach identified several new mappings with improved delay. To the best of our knowledge, this is the first application of exact synthesis realized on commercial FPGA architecture. |
| Keywords |
| | Exact synthesis, Agilex, Stratix 10, multipliers. |
| Library reference |
| | Shupletsov M.S., Zhukov V.V., Gribok S.V., Ganusov I., Mestetskiy M.A., Lopunov M.A., Kuprash E.D. Exact Synthesis of Low Precision Multipliers for Intel FPGAs // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 3. P. 212-218. doi:10.31114/2078-7707-2022-3-212-218 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2022/pdf/D037.pdf |
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