| The Optimal Algorithm for Generating a Complete Test for Checking the Simplest Single Logical-Dynamic Faults for an N-Input Combinational Device |
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| Authors |
| | Levitskiy D.O. |
| Date of publication |
| | 2022 |
| DOI |
| | 10.31114/2078-7707-2022-2-16-19 |
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| Abstract |
| | The question of the minimum length of a complete test for checking all the simplest single logical-dynamic (LD) faults [3,4] for an N-input combinational device is investigated. LD failure is expressed in the delay of the switching signal at a given point for more than one cycle. At the same time, switching delays from 0 to 1 and from 1 to 0 are different faults. An optimal algorithm for generating a complete LD test of exactly the minimum length is described, a C++ program that implements this algorithm and part of the constructed test is given. |
| Keywords |
| | testing, logical-dynamic faults, binary combinational circuits, algorithm for constructing a minimum length test, technical diagnostics. |
| Library reference |
| | Levitskiy D.O. The Optimal Algorithm for Generating a Complete Test for Checking the Simplest Single Logical-Dynamic Faults for an N-Input Combinational Device // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 2. P. 16-19. doi:10.31114/2078-7707-2022-2-16-19 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2022/pdf/D015.pdf |
