| Estimating of the Power Consumption of Combinational CMOS Circuits Based on Logic VHDL Simulation |
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| Authors |
| | Bibilo P.N. |
| | Audzeyeu M.A. |
| | Kirienko N.A. |
| Date of publication |
| | 2022 |
| DOI |
| | 10.31114/2078-7707-2022-2-9-15 |
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| Abstract |
| | Estimating of the power consumption using VHDL simulation is based on the use of modified VHDL models of circuit elements. Models take into account not only the functionality of the elements, but also the time delays of the elements. It is also required to modify the netlist of the circuit - to add parameters that describe the loads of each of the elements for outputs and inputs. The netlist of the circuit and the corresponding SDF file describing the delays of the circuit elements are obtained as a result of the synthesis of this circuit in the CMOS element library. The synthesis is performed in the LeonardoSpectrum (Mentor Graphics firm) software package. VHDL simulation is done in the Questa Sim software package using an SDF file. The power consumption estimation is performed by a separate process. The main purpose of this process is as follows. Previous and new combinations of element input states are determined using parameters whose values for each circuit component are transferred from the SDF file during simulation. Then, using these values and the values of load capacities, the power consumption of the element in the current cycle of circuit simulation is calculated. The result of VHDL simulation is a sequence of circuit power consumption values in each of the circuit simulation cycles and a calculated estimate of the circuit power consumption on a given test. Pseudorandom test sets with equiprobable values of zeros and ones are used as tests. The experiment was carried out on several streams of logic circuits. As a result of experiments, it was found that VHDL simulation reduces the time for calculating consumed currents by several orders of magnitude. VHDL simulations most often result in upper current estimates compared to the reference values produced by Accusim II analog Spice simulations. |
| Keywords |
| | logical circuit, synthesis, logical and circuit simulation, power consumption estimates, VHDL, CMOS VLSI. |
| Library reference |
| | Bibilo P.N., Audzeyeu M.A., Kirienko N.A. Estimating of the Power Consumption of Combinational CMOS Circuits Based on Logic VHDL Simulation // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 2. P. 9-15. doi:10.31114/2078-7707-2022-2-9-15 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2022/pdf/D012.pdf |
