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Multibank memory bandwidth analysis in on-chip system
Authors
	Voronov A.V.
	Voronov R.V.
	Iliasov R.F.
Date of publication
	2021
DOI
	10.31114/2078-7707-2021-4-99-105
Abstract
	nowadays, memory on a chip is one of the main components of microelectronic design. Usually, field-programmable gate arrays (FPGAs) are equipped with three block configurations of RAM: Single Port, Pseudo Dual Port, and Dual Port. This article discusses the development of a multiport memory design based on the principle of request arbitration, then it was redesigned in multibank memory. The purpose of the study is to analyze the transaction delay, with different numbers of ports and banks. The Pseudo Dual Port BRAM was chosen as the basis of the design. Using this type of memory block allows separating the read and writing ports separately because of their independent operation. In the process of creating multiport memory, it is necessary to solve the problem of conflicts that occur when a read or write requests are made on two ports simultaneously. This problem is caused by the limitation of the standard memory block. There are two general principles for solving this problem: memory duplication and request delay. The advantages and disadvantages of each option were considered. Finally, the bandwidth of the multibank memory was evaluated as a function of the number of ports and the number of banks. The bandwidth was estimated by measuring the average transaction processing time on 3 different tests. It was concluded that the optimal number of banks should not be less than half the number of ports.
Keywords
	multiport memory, multibank memory, memory arbitration, valid/ready interface.
Library reference
	Voronov A.V., Voronov R.V., Iliasov R.F. Multibank memory bandwidth analysis in on-chip system // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 4. P. 99-105. doi:10.31114/2078-7707-2021-4-99-105
URL of paper
	http://www.mes-conference.ru/data/year2021/pdf/D077.pdf