| Reliability-Driven Logic Synthesis Using Arbitrary Standard Cell Library |
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| Authors |
| | Telpukhov D.V. |
| | Nadolenko V.V. |
| Date of publication |
| | 2021 |
| DOI |
| | 10.31114/2078-7707-2021-4-52-58 |
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| Abstract |
| | the following paper presents logic synthesis algorithm with reliability optimization using arbitrary standard cell library. It takes a circuit in AIG format and cell library as input and returns synthesized Verilog netlist. Several reliability metrics to drive the algorithm are presented. These metrics take into account logical masking mechanism and differ by their precision levels. Presented algorithm is based on tree covering modified to optimize reliability characteristics. Tracking possible signal paths dynamically enables fast and precise goal function evaluation which is crucial for scalability. ISCAS’85 benchmark circuits were used for algorithm testing. AIGs for those circuits were generated via ABC tool. Finally, test circuits were used as input for resynthesis algorithm improving reliability. Experimental results show that modifying logic synthesis step favors resynthesis efficiency. |
| Keywords |
| | SET, tree covering, logic synthesis, resynthesis, reliability, observability, ODC |
| Library reference |
| | Telpukhov D.V., Nadolenko V.V. Reliability-Driven Logic Synthesis Using Arbitrary Standard Cell Library // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 4. P. 52-58. doi:10.31114/2078-7707-2021-4-52-58 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2021/pdf/D034.pdf |
