| Functional coverage verification methodology for data flow control verification in systems on a chip using SystemVerilog and examples of the interface with the AXI-Stream protocol |
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| Authors |
| | Latypov M. |
| | Starodumov A.A. |
| | Iliasov R.F. |
| Date of publication |
| | 2021 |
| DOI |
| | 10.31114/2078-7707-2021-3-71-75 |
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| Abstract |
| | Functional verification is the process of demonstrating the functional correctness of a design with respect to the design specifications. Functional verification does not confirm the correctness of the design specification and assumes that the design specification is correct. Functional coverage is a technology that measures how much of the original design specification has been implemented. Functional coverage has been used in software development for quite some time. The article shows the essence of the functional coverage based on the interface AXI-Stream. Functional coverage techniques are used not only in electronics design, but also in embedded software design. After the introduction of the functional version in System Verilog. Therefore, many companies have implemented this design process, which is mandatory for modern chips. One uncovered scenario could lead to an error requiring the chip to be re-fabricated at the factory, costing companies financial losses in delayed chip release and manufacturing costs. |
| Keywords |
| | functional verification, functional coverage, AXI-Stream. |
| Library reference |
| | Latypov M., Starodumov A.A., Iliasov R.F. Functional coverage verification methodology for data flow control verification in systems on a chip using SystemVerilog and examples of the interface with the AXI-Stream protocol // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 3. P. 71-75. doi:10.31114/2078-7707-2021-3-71-75 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2021/pdf/D033.pdf |
