Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference

Methodology of calculating dependent timing constraints for libraries of standard digital cells
Authors
	Ilin S.A.
	Lastochkin O.V.
	Ishchenko N.A.
Date of publication
	2021
DOI
	10.31114/2078-7707-2021-2-17-22
Abstract
	One of the most important problems of modern Systems-on-Chip (SoC) is increasing the clock frequency. There are various ways to solve this problem. This article discusses various ways to define setup and hold timing constraints for sequential circuits. Presented technique allows to reduce pessimism when calculating dependent timing constraints. The study found that the dependent edge (setup edge for dependent-setup and hold edge for dependent-hold) is sensitive to the position of the restrained edge relative to the position of the CLK clock. If the fixed edge (hold edge for dependent-setup and setup edge for dependent-hold) was changed by just a few picoseconds, this will allow the dependent edge to be reduced by dozens of picoseconds during the optimization stage. Thus, by changing the position of the locked edge, you can find the minimum value of the setup + hold sum. The value that was added to the fixed edge is called margin. Synopsys SiliconSmart has Independent and Dependent modes, the Dependent-Setup and Dependent-Hold modes are supported for calculating timing constraints [7]. For example, in Dependent-Setup, the fixed edge is the front associated with hold, and it is to this edge that the margin was added. The proposed technique consists of four stages: 1. Calculation of timing constraints in the Independent and Dependent modes to determine the boundaries of the search area for the margin value; 2. Separately are the margin values for setup from the Dependent-Hold mode; 3. Separately are the values for the hold margin, from the Dependent-Setup mode; 4. For each of the modes, a margin was selected that corresponds to the minimum amount of setup + hold. Algorithm is executed twice for the amount rise setup + fall hold and the amount fall setup + rise hold. Since when developing standard cells, common basic circuit solutions of the main nodes are used [8], the authors consider it possible to use a single margin value for all sequential cells. This article discusses the main features of the methods for characterizing timing constraints, analyzes their advantages and disadvantages. A comparison of the characterization modes was carried out using the example of a synchronous D-flip-flop clocked by the leading edge using the Synopsys SiliconSmart CAD system. This technique allows you to get more realistic values of timing constraints.
Keywords
	flip-flop, frequency, timing constraints, digital library, standard cell library, design flow; nanometer technology, system-on-a-chip (SoC).
Library reference
	Ilin S.A., Lastochkin O.V., Ishchenko N.A. Methodology of calculating dependent timing constraints for libraries of standard digital cells // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 2. P. 17-22. doi:10.31114/2078-7707-2021-2-17-22
URL of paper
	http://www.mes-conference.ru/data/year2021/pdf/D023.pdf