| ASMD-FSMD Technique for Digital Device Design |
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| Authors |
| | Salauyou V.V. |
| Date of publication |
| | 2021 |
| DOI |
| | 10.31114/2078-7707-2021-2-9-16 |
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| Abstract |
| | Recently, there has been an increase in the complexity of digital device designs and an increase in the requirements for the design time and the design reliability. One of the directions for solving this problem is developing new tech-niques designing digital devices. The paper proposes a tech-nique for designing digital devices based on finite state ma-chines with datapath (FSMD), when the functioning of the device is described in the form of an algorithm state ma-chine with datapath (ASMD) chart and is described in Veri-log HDL. The ASMD-FSMD technique is compared with the traditional approach when designing synchronous multipli-ers and PIC processors on the field programmable gate ar-ray (FPGA). Methods for increasing the performance of digital devices using the ASMD-FSMD technique are shown. The ASMD-FSMD technique, compared to the traditional approach, allows in most cases to reduce the area (for some examples on 47%) and increase speed (for some examples by a factor 2.96). In addition, using the ASMD-FSMD tech-nique allows to reduce the design time by a factor 5-7. In conclusion, recommendations on the use of the ASMD-FSMD technique and possible directions for the further de-velopment of the ASMD-FSMD technique are presented. |
| Keywords |
| | digital device design technique, finite state machines with datapath (FSMD), algorithm state machine with datapath (ASMD) chart, Verilog HDL, field programmable gate array (FPGA). |
| Library reference |
| | Salauyou V.V. ASMD-FSMD Technique for Digital Device Design // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 2. P. 9-16. doi:10.31114/2078-7707-2021-2-9-16 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2021/pdf/D022.pdf |
