| Digital Block Mathematical Model for the Joint Hardware and Software/firmware Simulation System |
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| Authors |
| | Ivannikov A.D. |
| | Stempkovsky A.L. |
| Date of publication |
| | 2021 |
| DOI |
| | 10.31114/2078-7707-2021-1-2-8 |
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| Abstract |
| | Based on specific modern digital system features the complex structure for hardware/software functional-logical simulation is proposed. The simulation aim is the debugging of hardware and software co-functioning on design stage. Hardware mathematical model with two levels of logical signal representation are developed. Such a model takes into account the modern digital system features, e.g. bidirectional buses, high impedance state of pin signals, block internal memory. It is shown that hardware simulation can be fulfilled by logical equation system solving on each simulation step. |
| Keywords |
| | functional-logical simulation, design debugging, digital system design, hardware model |
| Library reference |
| | Ivannikov A.D., Stempkovsky A.L. Digital Block Mathematical Model for the Joint Hardware and Software/firmware Simulation System // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 1. P. 2-8. doi:10.31114/2078-7707-2021-1-2-8 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2021/pdf/D018.pdf |
