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Architecture and structural-topological features of bit-stream devices
Authors
	Bureneva O.I.
	Milakin A.D.
	Mironov S.E.
Date of publication
	2021
DOI
	10.31114/2078-7707-2021-3-122-129
Abstract
	The paper shows a generalized structural diagram of a bit-stream device and defines its main elements. Purpose. Determination of the main features of the bit-stream devices hardware implementation. Methods. Based on the derivation of the transfer characteristic formula, using the example of a multiplication-division device, it is shown how the operations can be implemented using increment/decrement operations. To determine the efficiency of the bit-stream multiplier-divider, its comparison with the traditional matrix implementation of the same function was perform. When implementing it on an FPGA, the authors determined the properties of the device by modeling: the device was designed in the VHDL and synthesized by the Quartus II CAD system. When implementing it in the form of custom VLSI fragments using original hierarchical compression tools, the topologies of bit-stream and matrix calculators were obtained. The obtained results. The document shows that: • bit-streaming devices have a regular structure; this ensures easy buildup with increasing bit depth; • the main elements of the bit-streaming devices are binary counters, varying which you can implement different functions; • bit-streaming devices are more economical in terms of hardware costs, while losing in terms of time characteristics, which is determined by the peculiarities of the bit-stream representation of information. Discussion. The considered bit-streaming devices can be used in inertial control systems, where the conversion time is not critical.
Keywords
	bit-stream devices, matrix computing devices, pipeline circuits, structural organization, layout implementation, multiplying-dividing device.
Library reference
	Bureneva O.I., Milakin A.D., Mironov S.E. Architecture and structural-topological features of bit-stream devices // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 3. P. 122-129. doi:10.31114/2078-7707-2021-3-122-129
URL of paper
	http://www.mes-conference.ru/data/year2021/pdf/D048.pdf