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Implementation of self-testing tools for DDR3 memory modules in Spartan3e FPGA
Authors
	Volobuev S.V.
	Ryabtsev V.G.
Date of publication
	2021
DOI
	10.31114/2078-7707-2021-1-70-76
Abstract
	Designing self-testing tools for memory modules is a method of developing additional tools that eliminate the need for external expensive diagnostic systems, the cost of which is many times higher than the cost of the memory modules themselves. The implementation of self-testing tools increases the percentage of fault coverage, since testing is performed at operating frequencies, and no external test equipment is required. The paper describes the architecture of self-testing tools for DDR3 memory modules and features of the procedures for their implementation in programmable logic circuits. The project of self-testing tools for DDR3 memory modules is implemented in the XC3S500E FPGA of the Spartan3e family. The applied hardware-firmware method of forming tests combines high performance with low hardware costs, while reducing the memory capacity for storing test programs of the Marsh family. The structure of the system of commands for self-testing tools has been developed, which provides parallel encoding of working operations for accessing the tested memory and generating address and data codes. The diagnostic properties of the generated tests are improved due to their execution without skipping the clock cycles of accessing the memory module under test. The features of the design route are revealed, which defines the stages of design procedures used at all stages of development, from the development and formalization of the idea to the testing of finished samples. The project of self-testing tools for DDR3 memory modules uses libraries of logic elements that adapt to the schematic representation of the components. The results of prototype design with the implementation of the project on the FPGA allow you to check the correctness of design decisions on the composition and structure, which can be implemented in the future in a ready-made high-class application in the form of a custom large integrated circuit.
Keywords
	self-testing tools, the counter model, memory modules, the format of commands and micro-operations.
Library reference
	Volobuev S.V., Ryabtsev V.G. Implementation of self-testing tools for DDR3 memory modules in Spartan3e FPGA // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 1. P. 70-76. doi:10.31114/2078-7707-2021-1-70-76
URL of paper
	http://www.mes-conference.ru/data/year2021/pdf/D001.pdf