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ASIAN - Self-Timed Logic Circuits Analysis Subsystem
Authors
	Rozhdestvenskij Yu.V.
	Morozov N.V.
	Stepchenkov Yu.A.
	Rogdestvenskene A.V.
Date of publication
	2006
Abstract
	Subject of the report - the analysis of the asynchronous circuits independence behaviour from the element delays. Such circuits are known as self-timed. The circuit is defined as the boolean equation sets (logic elements), satisfying to delays Maller hypothesis. The analysis is based on the transition diagram constructions covering all possible scheme states, and known as global state circuit analysis methods. The main advantage of these methods consists in their universality – opportunities of application for the all self-timed circuit class analysis. Subsystem ASIAN is the program complex, which have allowed repeatedly to reduce a time expense for the analysis procedure in comparison by existing analogues and, in essence, to realize the greatest possible analysis efficiency.
Keywords
	Self-timed circuits; classification analysis in global states; computer-aided design
Library reference
	Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov Yu.A., Rogdestvenskene A.V. ASIAN - Self-Timed Logic Circuits Analysis Subsystem // Problems of Perspective Microelectronic Systems Development - 2006. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2006. P. 158-162.
URL of paper
	http://www.mes-conference.ru/data/year2006/28.pdf