| Complex parameterization technology for topological projects of regular VLSI macroblocks |
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| Authors |
| | Mironov S.E. |
| | Andreev L.E. |
| | Zibarev K.M. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-3-35-40 |
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| Abstract |
| | Software and methods developed to parameterize the process of designing a layout of hierarchical VLSI fragments at all design levels.
Purpose. To develop methods and tools of the system of complex parameterization for designing a hierarchical VLSI layout with high packing density.
Methods. Technological and electric parameterization is provided by the algorithm of one-dimensional layout compaction based on the virtual grid. Layout parameterization is provided by combinatorial and graphs methods of placement and tracing. Schematic parameterization is implemented based on the principles of working with variables of an enumerated type. Structural parameterization and high density of packing are achieved by an original method of matching cells in terms of outputs size and location.
The obtained results. Development of a system and technology of complex parameterization of the layout projects of regular hierarchical fragments of the VLSI. The modular principle of organization of the developed system and the autonomy of its components ensure the convenience and simplicity of its development towards the improvement of methods of parameterization.
Discussion. Main directions of further development:
– Conversion of the compression system of the layout to more efficient in terms of packing density compaction algorithms with changing the shape of transistors;
– Development of interface tools for a graphical description of structural and layout plans of irregular hierarchical fragments of VLSI;
– Realization of the compaction mechanisms providing essential acceleration of processes of cells matching without losses in the density of packing. |
| Keywords |
| | complex layout parameterization, layout compaction, close-packed design, cells matching, layout generation. |
| Library reference |
| | Mironov S.E., Andreev L.E., Zibarev K.M. Complex parameterization technology for topological projects of regular VLSI macroblocks // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 35-40. doi:10.31114/2078-7707-2020-3-35-40 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D115.pdf |
