| Use of Formal Methods to Resolve Actual Problems of ASIC Design Verification |
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| Authors |
| | Sokhatski A.A. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-3-22-27 |
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| Abstract |
| | There are some critical problems of SoC Design Verification (DV) related to growing functional complexity including
- Time to Market: full enough verification takes too much time;
- Verification Quality: costly chips re-spins take place; bugs are escaping detection by traditional verification method
The paper describes:
1) How Formal Verification could help to resolve Time to Market problem by doing “left shift” of design – verification timeline involving designers to use Formal tool to initially clean up design
2) How Formal Verification helps to improve verification quality and avoid re-spins by detection of simulation – resistant bugs [1]
3) Example of Lookup Table Block, corner case bugs close to simulation – resistant bug concept detected by Formal Verification which will be difficult to catch by simulation; Formal Verification strategy for the block and used Formal techniques |
| Keywords |
| | SoC, Design Verification, Formal Verification, SystemVerilog, SVA. |
| Library reference |
| | Sokhatski A.A. Use of Formal Methods to Resolve Actual Problems of ASIC Design Verification // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 22-27. doi:10.31114/2078-7707-2020-3-22-27 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D106.pdf |
