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Atomic instructions random tests generation using lock contention analysis
Authors
	Grevtsev N.A.
	Chibisov P.A.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-3-57-64
Abstract
	Atomic operations functional verification is known to be a rather labour-intensive process because atomic operations cannot be tested with the help of stochastic test generation methods due to their unpredictable nature. Atomic operations are synchronization primitives used as building blocks for mutual exclusions, spinlocks, and thread execution barriers. There are numerous approaches proposing a variety of methods to analyze and reduce lock contention problems in software or in hardware. These approaches quantify the synchronization mechanisms execution overhead or assess the impact these primitives have on the completion time of multithreaded application. However, it is reasonable to create test cases with forced shared data areas between threads intentionally to test the interaction between cores. In the paper, we propose to apply all previous researches to increase the coverage of atomic operations functional verification. According to the mentioned methods, we run PARSEC benchmarks and Linux Kernel Lock Torture Test to estimate and find the most contented segments of code in these applications. The obtained knowledge has been applied for extension of our current test generator Ristretto to create test cases with random load/store and atomic instructions combinations to generate necessary stimulus. The discussed approach was successfully tried out in practice on the verification process of the RTL-model of dual-core microprocessor with SMP developed in SRISA RAS. The advantage of the technique is that there is no need to change verification strategy and process to adjust to a new project design.
Keywords
	lock contention, cache contention, atomic instructions, functional verification, random test generation, PARSEC benchmark, lock torture, test coverage, simulator.
Library reference
	Grevtsev N.A., Chibisov P.A. Atomic instructions random tests generation using lock contention analysis // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 57-64. doi:10.31114/2078-7707-2020-3-57-64
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D090.pdf