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The methodology of automated performance analysis of SoC interconnect subsystems, according to the SoC structure and application
Authors
	Zhezlov K.A.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-3-94-99
Abstract
	The paper describes the infrastructure and methods for checking an interconnect subsystem as a part of a SoC for compliance with performance requirements. The graph-based test scenarios generator is suggested as a part of the infrastructure being mentioned. Also the approach for developing basic performance tests is described. There is a description of a set of performance metrics and criteria, which are tested on several examples, detecting performance problems. The following factors are critical for evaluating the performance of a system, as well as for searching for its bottlenecks: a test scenario aimed at creating conditions for measuring performance, a way of representing, creating and executing this scenario, suitable for reproducing errors in the future, and a performance evaluation methodic. The most convenient for solving the problems of the creation and execution of the test scenario is its presentation as a graph. This approach allows you to create a scenario that operates with transactions or even data flows, which allows you to transfer the test description to a higher level of abstraction. The graph-based approach describes a test scenario as an acyclic directed graph of transactions, the vertices of the graph are the transactions themselves, and the edges are the dependencies between them. This approach makes the test scenario reusable and error reproducible. Calculation of performance metrics and evaluation of criteria make it easier to evaluate the interconnect subsystem performance and find its bottlenecks.
Keywords
	SoC, verification, performance analysis, usage scenarios, system level verification, standalone verification, high-level model, graph-based approach, performance metrics
Library reference
	Zhezlov K.A. The methodology of automated performance analysis of SoC interconnect subsystems, according to the SoC structure and application // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 94-99. doi:10.31114/2078-7707-2020-3-94-99
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D077.pdf