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Multi-bit flip-flop usage features to reduce power in nanotechnologies
Authors
	Kalashnikov V.S.
	Semenov M.Y.
	Titov Y.A.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-3-180-187
Abstract
	System-on-Chips (SoC) designers use different techniques to reduce power consumption of their designs. Generally these methods can be divided into two categories. The first category includes techniques which can use various technology options for example different Voltage threshold (VT) options. The second category contains different circuit design methods for example increased gate length cells to reduce leakage power. One of the effective ways to reduce total power is the usage of Multi-bit Flip-flops (MBFFs). The results of comparison and application of MBFFs have been presented in this article. Application features of MBFFs based on 16nm and 28nm technology nodes have been also described. Comparison analysis of MBFFs, implemented in 28nm standard cell libraries, has been done in Chapter II. Stitched and Non-stitched architectures, its advantages and drawbacks have been considered. Cell-level comparison of MBFFs has shown the area and power benefits in compare with equivalent number of single-bit flip-flops. Chapter III describes how to proper use MBFFs in Digital Design Flow using Cadence CAD tools. Single-bit flip-flops can be replaced by MBFFs on SoC level keeping different options: - forced replacement which substitutes maximum as possible number of single-bit flip-flops and provides maximum benefits in power but makes worse timing characteristics, especially in critical timing paths; - replacement with keeping and analyzing of timing constraints for all paths, which provides balance between power and timing characteristics. In Chapter IV the statistical results of MBBFs usage in 16nm FinFET projects have been given. The results, presented in this article, have shown, confirmed and proved the usage of MBFFs as effective low-power solution.
Keywords
	flip-flop, Multi-bit flip-flop (MBFF), power consumption, digital library, standard cell library, digital design flow, nanotechnology, System-on-Chip (SoC), low power design
Library reference
	Kalashnikov V.S., Semenov M.Y., Titov Y.A. Multi-bit flip-flop usage features to reduce power in nanotechnologies // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 180-187. doi:10.31114/2078-7707-2020-3-180-187
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D074.pdf