| Digital Controlled Oscillator for All-Digital Phase-Locked Loop Circuit |
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| Authors |
| | Khalirbaginov R.I. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-3-212-217 |
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| Abstract |
| | A new design methodology of digitally controlled oscillator based on standard library cells is presented. The methodology includes the design of a scalable architecture to enable design automation. By analyzing the parameters of the circuit at an early stage of designing, the labor involved in developing such circuits can be reduced. The proposed oscillator architecture combines simplicity of design and high resolution with a wide dynamic range of tuning the output frequency. The basis for designing the oscillator circuit is the division into a coarse and fine-tuning. This approach allows to isolate parts of unused logic when operating at maximum output frequency, as well as expand the dynamic range without compromising maximum frequency. In the design of fine-tuning circuit, a new method was applied that uses the difference in path delay within a standard library cell. Based on the proposed methodology, a digitally controlled oscillator was designed and synthesized into the CMOS 90nm library. A linear characteristic of the output frequency versus control code is obtained, the resolution of the oscillator is 16 ps, and the dynamic range is from 150 to 700 MHz. |
| Keywords |
| | digital controlled oscillator, phase locked loop, standard cell library, coarse and fine-tuning, delay path. |
| Library reference |
| | Khalirbaginov R.I. Digital Controlled Oscillator for All-Digital Phase-Locked Loop Circuit // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 212-217. doi:10.31114/2078-7707-2020-3-212-217 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D073.pdf |
