| Analysing Chip Multiprocessor Scalability Using Trace-Based Simulation |
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| Authors |
| | Nedbailo Yu.A. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-3-87-93 |
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| Abstract |
| | As chip technology advances, the number of cores in mainstream chip multiprocessors (CMP) increases, so chips with hundreds of cores may become common within a decade. One of the challenges this trend sets to computer architects is to make the current CMP designs scalable to larger numbers of cores. A set of optimizations and design decisions needs to be developed accordingly and a tool set that would allow us to predict how they may affect the performance of larger CMPs is therefore necessary. In this paper, we describe a trace-based simulation framework we devised for Elbrus microprocessor family and the estimates of how this microarchitecture may perform in 64- and 256-core configurations. |
| Keywords |
| | Elbrus processor architecture, software simulation, cycle-accurate simulator (CAS), many-core, memory subsystem, shared cache. |
| Library reference |
| | Nedbailo Yu.A. Analysing Chip Multiprocessor Scalability Using Trace-Based Simulation // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 87-93. doi:10.31114/2078-7707-2020-3-87-93 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D072.pdf |
