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Benchmarking Energy Efficiency of Libraries on FinFET 7nm
Authors
	Ilin S.A.
	Korshunov A.V.
	Garbulina T.V.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-4-169-173
Abstract
	The rapid development of FinFET technology in recent years has led to changes in the digital design process at all stages of the route. The quantization of the channel width of the transistor has led to changes in the circuitry and layout of the digital standard cells. Reducing the energy consumption of high-performance VLSI systems has led to the need to develop new methods for the automated design of autonomous (self-feeding) circuits. The main task in developing such schemes is to find a compromise between energy consumption and performance. The article provides a comparative analysis of changes in performance and power consumption while reducing the supply voltage using the FinFET technology as an example with 7 nm node. The progress of CAD tools for digital design flow, due to technological scaling, has led to the need to take into account the features of standard cells at the earliest stages of design. This approach reduces the time spent on developing the library by introducing additional restrictions and reducing the number of studied options for schemes. The main requirement for such models is the balance between speed and accuracy, for which you must first identify the nature of the dependencies between the parameters of the transistors and the key characteristics of the circuit. Methods based on such models can be easily integrated into the tools of logical and layout synthesis, which will allow to evaluate the delay [4] and the power of the circuit. Currently, the main works are devoted to the development of models for the quick calculation of timing parameters, while power and leakage ones are considered to a lesser extent. The base for the study is a library of standard cells based on 7 nm FinFET transistors from ARM. [9] The library supports some threshold voltage (RVT / LVT / SLVT). For all three options, Liberty files were obtained for the nominal supply voltage (0.7 V) and three variation for reduced voltage: 0.4 / 0.5 / 0.6 V, respectively. An analysis of the experimental results showed that, on average, a decrease in the supply voltage leads to a noticeable decrease in speed, power consumption, and leakage power, while this trend is more noticeable for RVT library and less for LVT / SLVT libraries. A comparative analysis of the results suggests that the decrease supply voltage of more than 30% does not have practical sense. A further decrease voltage leads to an even more significant decrease in performance, with a relatively small gain in power consumption and leakage. Thus, voltage reduction to critical values can only be considered for specialized applications. In addition, the analysis of the experimental results showed: despite the fact that at voltages close to nominal, the power consumption depends in power of 2 on the supply voltage, when switching to ultra-low voltages, this dependence is stronger and the power depends on the voltage in power of 3,5-4.
Keywords
	FinFET, energy efficiency, standard cell libraries, dynamic power, leakage.
Library reference
	Ilin S.A., Korshunov A.V., Garbulina T.V. Benchmarking Energy Efficiency of Libraries on FinFET 7nm // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 4. P. 169-173. doi:10.31114/2078-7707-2020-4-169-173
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D085.pdf