| Adaptation process of System-on-a-Chip RTL-description for distributed emulation system |
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| Authors |
| | Petrov A.N. |
| | Yurlin S.V. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-4-45-50 |
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| Abstract |
| | multi-FPGA distributed emulation systems are commonly used for functional verification of System-on-a-Chip. However, using such systems poses a problem of adaptation RTL-description for use in multi-FPGA system. This article outlines common issues for transition process towards functional verification of System-on-a-Chip using multi-FPGA distributed emulation system from the developer point of view. Article also introduces a method of adaptation, currently used in JCT “MCST”. Adaptation process presents following problems: distributing SoC description across multiple FPGAs, configuring inter-FPGA connections according to RTL logic, generating FPGA firmware. Proposed method solves these problems. It consists of five stages. First stage: preparation - setting up runtime for implementation and limited flattening of SoC hierarchy. Second stage - partition and assembly – creating interconnected logic modules containing original RTL, FPGA wrappers and top-level modules. Model generation – generating RTL model of distributed emulation system. Post-processing – correcting of CAD artifacts and making generated RTL more human-readable for further modification. FPGA project generation – creating FPGA projects from project templates for further firmware generation. |
| Keywords |
| | emulation, FPGA, microprocessor, emulation systems. |
| Library reference |
| | Petrov A.N., Yurlin S.V. Adaptation process of System-on-a-Chip RTL-description for distributed emulation system // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 4. P. 45-50. doi:10.31114/2078-7707-2020-4-45-50 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D059.pdf |
