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Configuration of microelectronic means on the basis of iterative clusterization taking into account time delays
Authors
	Barinov S.V.
	Kurejchik V.M.
	Gladkov L.A.
Date of publication
	2006
Abstract
	In article the problem of configuration of combinational schemes on the basis of iterative clasterization taking into account time delays and spatial restrictions is considered. In introduction the urgency of working out of new algorithms for the decision of a problem of configuration of combinational schemes in connection with a wide circulation of schemes with FPGA architecture is proved. The description of mathematical model of the switching scheme in the form of the acyclic focused count is resulted. Also the description to the process clasterization of the graph is given. The new multilevel approach to the decision of a problem of configuration on the basis of a combination of methods clasterization and convolutions is offered. The block diagramme and a pseudo-code of the developed algorithm is resulted.
Keywords
	Layout, the hypergraph, the combinational scheme, clasterization, time delays, a delay of a signal, convolution of the graph
Library reference
	Barinov S.V., Kurejchik V.M., Gladkov L.A. Configuration of microelectronic means on the basis of iterative clusterization taking into account time delays // Problems of Perspective Microelectronic Systems Development - 2006. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2006. P. 130-134.
URL of paper
	http://www.mes-conference.ru/data/year2006/22.pdf